Copper Interconnect Technology by Tapan Gupta

By Tapan Gupta

Since total circuit functionality has depended totally on transistor houses, earlier efforts to reinforce circuit and approach pace have been enthusiastic about transistors to boot. over the past decade, in spite of the fact that, the parasitic resistance, capacitance, and inductance linked to interconnections started to impact circuit functionality and may be the first elements within the evolution of nanoscale ULSI know-how. simply because steel conductivity and resistance to electromigration of bulk copper (Cu) are higher than aluminum, use of copper and low-k fabrics now prevails within the foreign microelectronics undefined. even though, because the function dimension of the Cu-lines forming interconnects is scaled, resistivity of the traces raises. while electromigration and stress-induced voids as a result of elevated present density develop into major reliability concerns. even if copper/low-k know-how has turn into particularly mature, there's no unmarried ebook to be had at the promise and demanding situations of those next-generation applied sciences. during this publication, a pace-setter within the box describes complicated laser structures with decrease radiation wavelengths, photolithography fabrics, and mathematical modeling ways to deal with the demanding situations of Cu-interconnect know-how.

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Recently, polymers are being used to fabricate light emitting devices (LEDs) and transistors [140–141]. 39, shows the structure of an organic light emitting diode (OLED) where a thin layer of organic material (polymer) is sandwiched between anode and cathode layers. 40 shows a thin film transistor (TFT) fabricated on a flexible polymeric substrate, which is reported to achieve charge carrier mobilities in excess 32 1 Introduction Fig. 38 Top down scanning electron microscopic picture of a 40 nm feature created with DUV photoresist over a silicon wafer (Reprinted with permission, Solid State Technology (SST), July 200, p.

July 2004 p. 95) induced stress is related to the dimension of the line. 18 shows the stress and electromigration in Cu-interconnect as the geometry of the interconnect shrinks. 1 Multilayer Metal Architecture Interconnect delays are increasingly dominating IC performance in spite of copperlow-K dielectric systems, and it is expected that the interconnect delay will be substantial below 130 nm node technology [10,50]. Therefore the need exists for an alternative technology to overcome the problem.

The idea of superconductivity and the invention of high-temperature superconductors (high Tc ) in 1987 brought new hopes in the field of interconnect technology [198–202]. Bulk superconductivity based on a copper–oxygen array is an important structural feature (Fig. 56). But neither the metallic bond, nor copper–oxygen bonding guarantees superconductivity [203]. 57 shows a picture of a single crystal of Y1 Ba2 Cu3 O1–x superconductor. 46 1 Introduction Fig. 89Å Fig. 57 A single crystal of Y1 Ba2 Cu3 O1–x (Photo courtesy, IBM Research) There is an another class of superconductors which is known as a layered superconductor [204] where we have two interpenetrating perpendicular vortex lattices consisting of Josephson vortices (JVs) and pancake vortices (PVs).

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